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L. Ribas, Riera, J., Pérez, J. M., J. Saiz,, Carrabina, J., and Terés, L., “Automatic Pattern Generation for the Electrical Characterization of Digital Modules”, Microprocessing and Microprogramming , vol. 39, pp. 255-258, 1993.

D

J. Riera, Ribas, L., Velasco, A. J., and Carrabina, J., “Deriving Cost Functions from Cell Libraries and Real IC's to real Area-Power-Delay Trade-off in Early Stages of Logic Synthesis.”, Journal of Systems Architecture , vol. 43 , pp. 119-122, 1997.

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