Found 124 results
Author Title Type [ Year(Desc)]
Filters: Author is Carrabina, J.  [Clear All Filters]
G. Talavera, Jayapala, M., Carrabina, J., and Cathoor, F., Address Generation Optimization for Embedded High-Performance Processors: A Survey, Journal of Signal Processing Systems for Signal Image and Video Technology (formerly the Journal of VLSI Signal Processing Systems for Signal Image and Video Technology), 2008.
J. Joven, Font-Bach, D., Castells-Rufas, D., Martínez, R., Terés, L., and Carrabina, J., xENoC - An eXperimental Network-on-Chip Environment for parallel distributed computing on NoC-based MPSoC architectures, 16th Euromicro Int. Conf. on Parallel, Distributed and network-based Processing (PDP’08). Toulouse, Francia, 2008.
M. Moreno-Berengue, Talavera, G., Rodriguez-Alsina, A., and Carrabina, J., Address generation unit for multimedia applications on application specific instruction set processors, 6th Annual Conference of the IEEE Industrial Electronics Society. IECON-2010. Phoenix, Arizona, USA, 2010.


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