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L
L. Ribas, Castells-Rufas, D., and Carrabina, J., A Linear Sorter Core based on a Programmable Register File, Proc. of XIX Conference on Design of Circuits and Integrated Systems. Bordeaux, France , 2004.
J
D. Castells-Rufas and Carrabina, J., Jumble: A Hardware-in-the-Loop Simulation System for JHDL, 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2007. FCCM 2007. . p. v, 2007.

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