Publicacions

Found 2 results
Author Title Type [ Year(Asc)]
Filters: Author is Veredas, F. J.  [Clear All Filters]
2005
F. J. Veredas and Carrabina, J., Power Dissipation Impact of the Technology Mapping Synthesis on Look-up Table Architectures, Proc. 15th International Workshop PATMOS 2005, vol. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. . Leuven, 2005.
F. J. Veredas and Carrabina, J., Power Dissipation Impact of the Technology Mapping Synthesis on FieldProgrammable Gate Arrays, V Jornadas de Computación Reconfigurable y Aplicaciones. JCRA 2005. Integrado en CEDI2005. Granada, 2005.
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